1. Field of the Invention
The present invention relates to a display, and more particularly, it relates to a display comprising a shift register circuit.
2. Description of the Background Art
A display comprising a shift register circuit is known in general, as disclosed in Japanese Patent Laying-Open No. 2005-17973, for example.
FIG. 18 is a circuit diagram for illustrating the circuit structure of a shift register circuit driving drain lines of the exemplary conventional display disclosed in the aforementioned Japanese Patent Laying-Open No. 2005-17973. Referring to FIG. 18, the shift register circuit driving the drain lines of the exemplary conventional display is provided with a plurality of stages of shift register circuit portions 1001 to 1003. The first-stage shift register circuit portion 1001 is constituted of a precedent first circuit portion 1001a and a subsequent second circuit portion 1001b. The first circuit portion 1001a of the first-stage shift register circuit portion 1001 includes n-channel transistors NT501 to NT503, a diode-connected n-channel transistor NT504 and a capacitor C501. The second circuit portion 1001b of the first-stage shift register circuit portion 1001 includes n-channel transistors NT505 to NT507, a diode-connected n-channel transistor NT508 and a capacitor C502. The n-channel transistors NT501 to NT508 are hereinafter referred to as transistors NT501 to NT508 respectively.
In the first circuit portion 1001a, the drain and the source of the transistor NT501 are connected to a higher voltage supply source VDD and the drain of the transistor NT502 respectively. The gate of the transistor NT501 is connected to a node ND501. The source of the transistor NT502 is connected to a lower voltage supply source VBB. The gate of the transistor NT502 is supplied with a start signal ST. The transistor NT503 is connected between the node ND501 connected with the gate of the transistor NT501 and the lower voltage supply source VBB. The gate of the transistor NT503 is supplied with the start signal ST. The capacitor C501 is connected between the gate and the source of the transistor NT501. The diode-connected transistor NT504 is connected between the node ND501 connected with the gate of the transistor NT501 and a clock signal line CLK1.
In the second circuit portion 1001b, the drain of the transistor NT505 is connected to the higher voltage supply source VDD. The source of the transistor NT505 is connected with the drain of the transistor NT506. The gate of the transistor NT505 is connected to a node ND503. The source of the transistor NT506 is connected to the lower voltage supply source VBB. The gate of the transistor NT506 is connected to a node ND502 provided between the transistors NT501 and NT502 of the first circuit portion 1001a. 
The transistor NT507 is connected between the node ND503 connected with the gate of the transistor NT505 and the lower voltage supply source VBB. The gate of the transistor NT507 is connected to the node ND502 of the first circuit portion 1001a. The capacitor C502 is connected between the gate and the source of the transistor NT505. The diode-connected transistor NT508 is connected between the node ND503 connected with the gate of the transistor NT505 and the clock signal line CLK1.
The first-stage shift register circuit portion 1001 outputs a shift output signal SR501 from a node ND504 (output node) provided between the source of the transistor NT505 and the drain of the transistor NT506. The second- and third-stage shift register circuit portions 1002 and 1003 have circuit structures similar to that of the first-stage shift register circuit portion 1001. In other words, the second-stage shift register circuit portion 1002 includes first and second circuit portions 1002a and 1002b having circuit structures similar to those of the first and second circuit portions 1001a and 1001b of the first-stage shift register circuit portion 1001 respectively. The first circuit portion 1002a of the second-stage shift register circuit portion 1002 is connected to the node ND504 (output node) of the second circuit portion 1001b of the first-stage shift register circuit portion 1001. Thus, the first circuit portion 1002a of the second-stage shift register circuit portion 1002 receives the shift output signal SR501 from the first-stage shift register circuit portion 1001. A clock signal line (CLK2) supplying a clock signal CLK2 different in timing from a clock signal CLK1 supplied to the first-stage shift register circuit portion 1001 is connected to the second-stage shift register circuit portion 1002. The second-stage shift register circuit portion 1002 outputs a shift output signal SR502 from a node ND504 (output node) of the second circuit portion 1002b. 
The third-stage shift register circuit portion 1003 includes first and second circuit portions 1003a and 1003b having circuit structures similar to those of the first and second circuit portions 1001a and 1001b of the first-stage shift register circuit portion 1001 respectively. The first circuit portion 1003a of the third-stage shift register circuit portion 1003 is connected to the node ND504 (output node) of the second circuit portion 1002b of the second-stage shift register circuit portion 1002. Thus, the first circuit portion 1003a of the third-stage shift register circuit portion 1003 receives the shift output signal SR502 from the second-stage shift register circuit portion 1002. The clock signal line (CLK1) supplying the same clock signal CLK1 as that supplied to the first-stage shift register circuit portion 1001 is connected to the third-stage shift register circuit portion 1003. The third-stage shift register circuit portion 1003 outputs a shift output signal SR503 from a node ND504 (output node) of the second circuit portion 1003b. This shift output signal SR503 is input in a first circuit portion of a subsequent shift register circuit portion (not shown).
The nodes ND504 of the shift register circuit portions 1001 to 1003 are connected to a horizontal switch 1100. More specifically, the horizontal switch 1100 includes a plurality of transistors NT510 to NT512. The gates of the transistors NT510 to NT512 are connected to the nodes ND504 of the first- to third-stage shift register circuit portions 1001 to 1003 respectively. Thus, the shift output signals SR501 to SR503 from the first- to third-stage shift register circuit portions 1001 to 1003 are input in the gates of the transistors NT510 to NT512 of the horizontal switch 1100 respectively. The drains of the transistors NT510 to NT512 are connected to drain lines respectively. The sources of the transistors NT510 to NT512 are connected to a video signal line Video.
According to the aforementioned structure, the shift register circuit driving the drain lines of the exemplary conventional display inputs the shift output signals SR501 to SR503 shifted in timing for rising to high levels from each other in the gates of the transistors NT510 to NT512 of the horizontal switch 1100 respectively. Thus, the transistors NT510 to NT512 of the horizontal switch 1100 sequentially enter ON-states, whereby the display sequentially outputs video signals from the video signal line Video to the drain lines.
In the exemplary conventional display comprising the shift register circuit shown in FIG. 18, however, the voltage supply sources of the nodes ND504, i.e., the output nodes of the shift register circuit portions 1001 to 1003 disadvantageously reach instable levels between the higher and lower voltage supply sources VDD and VBB before the shift register circuit supplied with the higher and lower voltage supply sources VDD and VBB starts scanning. Thus, the transistors NT510 to NT512 of the horizontal switch 1100 having the gates connected to the nodes ND504 may disadvantageously enter ON-states at unintentional timing. In this case, the shift register circuit disadvantageously outputs the video signals from the video signal line Video to the drain lines through the ON-state transistors NT510 to NT512 at unintentional timing.